Detecting design geometries with a high correlation with yield detractors early on in the design process is a key for improving yield. Known approaches generate sitelists for Si inspections based on pattern matching of the patterns harvested by pattern classification of (optical rule check (ORC)/manufacturing rule check (MRC)/design rule check (DRC)/Si defect) markers at some fixed radius and fuzziness. However, these approaches lack precision and sensitivity. Even if a pattern association tree (PAT) approach is implemented, such methodology suffers from dependency on electronic design automation (EDA) vendor pattern classification licenses, which are expensive. In addition, due to the prohibitive cost of the EDA vendor pattern classification licenses and runtimes, only a subset of the ORC/MRC/DRC flagged locations, e.g., from the lower left corner of a design, are classified and used for sitelist generation for Si inspections. This leads to incomplete coverage of the variability detected by these ORC/MRC/DRC markers in the design. Moreover, none of the design for manufacturing (DFM) collateral decks, e.g., manufacturing analysis and scoring (MAS), target MAS (tMAS), routing signature analysis (RSA) back-end-of-line (BEOL), device profiling, design finishing-pattern optimization deck (DF-POP), advanced design rule check (DRC+), chemical mechanical polishing (CMP), critical area analysis (CAA), etc., flagged locations are directly used to drive Si inspections that can help to identify yield detractors. Further, the complex interactions that lead to defects are particularly hard to predict by using just one EDA vendor tool deck.
A need therefore exists for methodology and apparatus enabling capture of defects early on rather than as part of a later Si discovery process.